Lagrangian Relaxation Based Congestion Driven Analytical Placement

Analytical VLSI placement techniques achieved high solution quality and strong extensibility based on smooth approximation of placement objective and constraints. However, significant room still exist for VLSI placement to improve. We observe at least two sources of placement complexity and inaccuracy, namely, poor predictability for placement metrics and poor controllability of placement constraints. In particular, we observe that existing analytical placement techniques enhance the non-overlapping feasibility constraints by minimizing layout density deviation across a chip, which is an over-constraint, and propose congestion driven analytical placement for more effective placement feasibility enhancement and more accurate routing congestion control. Furthermore, we observe that analytical placement is an Lagrangian relaxation process, and apply Lagrangian relaxation techniques to analytical placement. Our experimental results show that our proposed congestion driven analytical placement achieves an average of 5.1% postlegalization wirelength reduction for 16 industry design and ISPD placement contest benchmark test cases compared with the existing cell density deviation minimization based analytical placement techniques, e.g., APlace [7].